As an active proponent of three-dimensional integrated circuits (3D ICs) for more than 7 years, Tezzaron® is gratified to see the near-universal recognition of this exciting technology. As more and more organizations invest in 3D IC research and development, Tezzaron welcomes the expanding opportunities for partnership and collaboration in 3D electronics.

This page provides a summary of the current state of 3D ICs. Other 3D structures such as MEMS and SiP are not addressed.

For papers and articles discussing 3D ICs, we recommend the following page at the website of the 3D-IC Alliance:
http://3d-ic.org/literature.html

The information on this page is gathered from trade publications, websites, and conference presentations. Please alert us to any corrections and updates at webmaster@tezzaron.com.

Wafer stacking, using copper bonding and standard "bulk" wafers; thru-silicon vias (TSV). Six different two-level devices were successfully produced in 2004. Four-wafer test stacks have been created; electrical connectivity has been verified in 3-wafer stacks; bulk wafers have been stacked with SOI wafers. Business offers 3D products, joint ventures, and licensing. (IAB, 2004; TechVenture 2004 thru 2007; VMIC 2004 thru 2007; Semicon West 2006; 3D-SIC 2007; IMAPS 2007)

Die-on-wafer stacking using room-temperature covalent bonding (silicon fusion) and direct oxide bonding. A two-wafer test stack was created, but primary emphasis is integrating known good dies (KGDs) onto wafers, producing two-level "chip pairs." Business offers heterogeneous substrates; chip stacking; custom 3D services. 3D SoC announced in 2005. (TechVenture 2004 thru 2007; MRS 2006; 3D-SIC 2007)

Die-on-die and die-on-wafer stacking using micro-bump bonding and/or deep through-silicon vias (TSV); commercial optical components and custom devices; working with DARPA. (TechVenture 2004 & 2006)

Permanent 3D memories, one-time-programmable (OTP); multiple memory layers built on a single wafer. OTP memories with eight layers were announced in 2001, first shipped in 2003, now being shipped in volume. (Matrix paper at VMIC 2005)

Wafer-on-wafer stacking with injection glue bonding, buried vias (tungsten or polysilicon), and "micro-bump" connectors. (TechVenture 2005 & 2006)

Die-on-die stacking; commercial memory and custom devices. (TechVenture 2004)

Through-silicon "drill-and-fill" via services including patterning, etching, thinning, die stacking.

3D-related services: wafer bumping, die placement, backgrinding, etc. (TechVenture 2006)

3D chip packaging, die stacking (TechVenture 2004, 2006 & 2007)

Thru-silicon via (TSV) R&D services; advanced vertical interconnects; custom through wafer via manufacturing and testing; low volume production runs. (TechVenture 2006)

Modeling tools for 3D silicon (TechVenture 2007)

Equipment for alignment and bonding, both chip-to-wafer and wafer-to-wafer. (TechVenture 2004 thru 2007; Semicon West 2005; IMAPS 2007)

"Pure Play" semiconductor foundry; provides models, tools, & support for 3D integrated designs. (TechVenture 2006)

Etch system for Thru-Silicon Vias (TSV). (TechVenture 2007.)

Die-to-wafer and wafer-to-wafer bonding equipment. (TechVenture 2006)

3D layout editor for stacked chip designs.

Process tools for 3D packaging; electrochemical copper deposition, etc.

EDA tools for 3D integrated circuit design and analysis; 3D circuit design services; working with Micro Magic; also working with DARPA. (VMIC 2005, TechVenture 2006, 3D-SIC 2007)

Copper interconnect, wafer prep, wafer level packaging. (IMAPS 2007)

Etch, deposition, and sealing systems.

Aligners, wafer and device bonders, and other 3D packaging tools. (TechVenture 2005 thru 2007; IMAPS 2007)

Consortium of integrated circuit designers, developers, and manufacturers; promotes standards for three-dimensional integrated circuits (3D ICs).

Research on 3D read-only memory chips.

Research on wafer stacking, interconnects, and wafer-scale heterogeneous 3D integration; partner with many other research groups. (TechVenture 2005)

Research on thru-silicon vias (TSV). (IMAPS 2007)

Research on 3D cell phone transmit module. (TechVenture 2004)

Japanese consortium. Developed a bulk wafer stacking process with Cu-Sn eutectic bonds and 10 um vias, successfully demonstrated on CCD wafers. (Effort ended in 2004.) Research on 3D sensors (with Sanyo Electric), chip-to-chip bonding, technology used in CCD camera. (TechVenture 2004 & 2007; 3D-SIC 2007).

Research on 3D memories and image sensors, using wafer stacking with metal bonding. (TechVenture 2006)

Research on 3D IC design tools. (TechVenture 2004, 2005, 2007)

Research on wafer-to-wafer and die-to-wafer stacking; self-assembly, direct bonding, and capillarity; 3D smart cards. (TechVenture 2005 & 2006, IMAPS 2007, IITC 2007)

Research on 3D wafer-level low-temperature circuit layering using SOI wafers; 3D electronic integration; crosstalk & heat issues; 3D FPGAs. Four-layer stack announced in 2005. ( VMIC 2004 thru 2007)

Funds special research, including 3D IC process technology, heterogeneous integration, 3D architectures, stacked FPGAs, and a "vertically interconnected sensor array" (VISA) with die-on-wafer stacking and polymer adhesive bonding. Funded two "multi-project wafer" runs, each with 3 stacked wafers; preliminary results in 2006 show some parts are functional. (TechVenture 2004 & 2005; VMIC 2007)

Precision processing tools for grinding, polishing, dicing. (3D-SIC 2007)

Research on high-density memories, including a 3D "bio-brain" concept; memory stack will use via-first construction, back-bumping,  interposer layer, and interface chip. (TechVenture 2006, 3D-SIC 2007)

A consortium of tech, tool, and materials companies; research into chip stacking with thru-silicon vias. (IMAPS 2007)

Research on vertical system integration, chip-in-polymer stacking, die-on-wafer stacking with solder bonds, flexible substrates, and 3D components (sensors, CPUs, memories). (TechVenture 2005 & 2007, MRS 2006, 3D-SIC 2007, IMAPS 2007)

Research on wafer-to-wafer bonding techniques. (TechVenture 2005 & 2006, IITC 2007)

Research on stacking techniques and 3D sensors. (TechVenture 2004)

Research on physical design, design tools, micro-architecture, and thermal and interconnect issues in 3D ICs.

Research on 3D architectures, thermal issues, routing, reliability, etc. Many papers and publications.

Research on 3D integration technologies, especially wafer stacking with TSV. (TechVenture 2007)

Research on wafer-level stacking of SOI wafers using oxide fusion bonding; Cu bonding; and die-on-wafer stacking, mounting small dies onto a larger "motherboard" die. Interconnects have been created on 4-wafer mechanical stacks. In 2007, announced a chip-stacked power amplifier with 100 direct metal connections. Other research on 3D design tools, test structures, methodology, process, infrastructure. (TechVenture 2004, 2005, 2007; VMIC 2005 thru 2007; MRS 2006; 3D-SIC 2007; IMAPS 2007)

Research on 3D approaches and enabling technologies, including die thinning, die stacking, chip-in-polymer stacking, and through-wafer vias. Runs APIC center (with other companies) to study interconnect. 2007, demonstrated wafer stacking with thru-silicon vias. (ISSCC 2004, TechVenture 2005 & 2006, IITC 2006, VMIC 2007)

Die-on-die "chip sandwich" stacking, using diffusion soldering, micro-bump bonding. Technique demonstrated in 2002; prototype security chip-card demonstrated November 2004. Also two-level die-on-wafer memory stacking and deep vias (with Fraunhofer). (TechVenture 2004 & 2007, MRS 2006, 3D-SIC 2007). 

Research on stacking, 3D interconnects, 3D components, copper bonding. Simulations of two-level processors indicate 15% speed improvement plus 15% power reduction. 2007, exploring through-silicon vias and 3D Flash. Also, research on stacking memory onto processor. (VMIC 2004, MRS 2006, TechVenture 2007)

Research on 3D IC process technology and thermal issues, 3D modular system integration, interconnects by die-edge metallization and thru-silicon (not thru-die) vias. Also sells 3D memory packages. (TechVenture 2004 & 2005, 3D-SIC 2007, VMIC 2007)

Research in substrates for vertical interconnect. (VMIC 2006)

Research into 3D for high performance computing; 3D interconnect; heterogeneous integration with covalent bonding; aluminum through-silicon vias have achieved aspect ratios of 16:1. (TechVenture 2005, VMIC 2006) 

Research on three-layer SOI wafer bonding with silicon handle and low-temperature oxide bonding; 3D image sensors and radar sensors; first image sensor tests in 2005. (TechVenture 2005, VMIC 2006 & 2007, MRS 2006)

Funds and operates research centers; its Interconnect Focus Center participates in 3D efforts. (TechVenture 2004)

Research on through-wafer 3D vertical interconnect (copper and optical), integrated passives, heterogeneous integration, vertical sensor arrays; working on various government and corporate programs. (TechVenture 2005)

Research on 3D memory using thru-wafer interconnects, a redistribution layer, solder balls, and epoxy encapsulation. Demonstrated 2-die stack. (MRS 2006)

Research on 3D IC layout issues, wafer stacking, high-density interconnect, copper bonding, oxide fusion bonding, using various types of wafers. Two-wafer stacks were announced in 1999; sensor design in 2001; four-wafer stacks in 2005. (IAB 2004; TechVenture 2004 & 2005; MRS 2006; 3D-SIC 2007)

Research on 3D stacking, sensors, memories, and packaging. (TechVenture 2004)

Research on 3D interconnect networks, architectures, & design rules. Working with DARPA. (VMIC 2006 & 2007, TechVenture 2006)

Research into 3D design and toolsets. (TechVenture 2006)

Monitors and reports on 3D IC technology. (TechVenture 2006)

Research on 3D IC design management and flow, thermal issues, verification and synthesis tools; lead contractor for DARPA project (2004).

Research on silicon layering, epitaxial growth.

Research on wafer stacking/bonding/thinning with standard wafers and/or SOI; dielectric adhesives for low-temperature bonding; magnetic alignment; copper bond pads; 3D power delivery; 3D SOI SRAMs; 3D optical interconnect. Interconnect process announced in 2003. (TechVenture 2004 thru 2007; VMIC 2004 thru 2007; MRS 2006)

Research on multi-layer memories. (TechVenture 2004)

Research on 3D die-to-wafer integration with polymer and Cu/Sn bonding; polygeneous integration; vertically integrated sensors and coherent light devices; working with DARPA. (TechVenture 2005 thru 2007; MRS 2006; 3D-SIC 2007; VMIC 2007)

Research on chip-on-chip and chip-on-wafer stacking for high-density memory; thru-silicon vias, micro-bumps. 8-chip NAND stack (prototype) announced in 2005. (TechVenture 2005 thru 2007)

Research on 3D interconnect, identified as a "top technical challenge" in its International Technology Roadmap for Semiconductors (ITRS) for 2005. Organized symposium "3D Chips: Critical and Practical Aspects of Manufacturing" in April 2004 and "3D Infrastructure Roadmap Workshop" in June 2005. 2007, working on industry roadmap and cost model for 3D chips with through-silicon vias. (TechVenture 2005 & 2007, VMIC 2006, 3D-SIC 2007)

Research on end-use market drivers for 3D components.  (TechVenture 2004)

Research on 3D packaging. (TechVenture 2004)

Coordinates academic "pre-competitive" research, including 3D process structures and 3D integration. (TechVenture 2005)

Research on 3D IC interconnects, integrity, performance, epitaxial growth, thermal issues, hybrid devices, 3D FPGAs, etc. (Great Lakes Symposium of VLSI, International Symposium on System Designs (ISPD), and IAB, all in 2004; VMIC 2004 thru 2007; TechVenture 2004 thru 2006)

Research on thru-silicon vias, micro-bumping, wafer thinning and bonding, 3D wafer level integration. (TechVenture 2004, 2006, & 2007; IMAPS 2007)

Research on wafer-level and chip-level alignment; covalent bonding; vertical communication bit-rates. (TechVenture 2006, IITC 2007)

Research on 3D interconnect: power, bandwidth, architectures. (TechVenture 2004)

Research on chip-in-polymer technology. (MRS 2006, IMAPS 2007)

Research on 3D chip-scale packaging. Hosted 3D packaging symposium in 2003. (TechVenture 2004 & 2007)

Research on 3D technology including wafer stacking with adhesive and micro-bump bonds; developed a 3D artificial retina, various 3-layer chips (with Mitsubishi, MIT, ZyCube). (VMIC 2004; TechVenture 2005)

Research on chip-stacking with copper bump bonding and through vias; 3D memory cells and CCDs (tested 2005); inter-level "crossbar" technology. (TechVenture 2004 thru 2007)

Research on 3D thermal-aware design tools (with DARPA, CFDRC). (VMIC 2006)

Research on wafer stacking; vertical connectors are applied to the die edges. (TechVenture 2007)

Research on 3D programmable "system-in-package" devices; working with DARPA. (TechVenture 2006)

Market Research, Analysis, Consulting, Reporting

(TechVenture 2007)

(TechVenture 2007)